`timescale 1ns / 1ps

reg clk;
reg rst;
wire [ 9 : 0 ] counter_result;

initial begin
    clk = 1'b0;
    rst_n = 1'b0;

    #500 rst_n = 1'b1;
end

always
    #10 clk = ~clk;

always @ (posedge clk)
    if (!rst_n) counter <= 10'b0;
    else counter <= counter + 10'b1;


